1. Field of the Invention
The present invention relates to a pattern data verification method, a pattern data creation method, an exposure mask manufacturing method, a semiconductor device manufacturing method, and a computer program product that are employed in a lithographic process.
2. Description of the Related Art
The progress in the semiconductor manufacturing technology in recent years is extremely remarkable, and semiconductor device having a size minimum of 70 nm is produced in large quantities. The miniaturization of semiconductor device is realized by rapid progress in fine pattern forming technology such as a mask process technology, an optical lithography technology, an etching technology, and the like.
In the days when pattern sizes have been sufficiently large, a pattern nearly same as the design pattern can be formed on the wafer by drawing a plane shape of a desired integrated circuit as a design pattern on a mask pattern, preparing a mask pattern which is faithful to the design pattern, transferring the mask pattern on the wafer by a projective optical system, and etching an underlying layer.
However, as the miniaturization of semiconductor device and integration of integrated circuit increase, forming the pattern faithfully is getting difficult in each process. As a result, the problem that a final finished dimension is not made to be as the same as a design pattern has been brought about.
One of the reasons for the above-described problem is that a layout disposition of other patterns disposed at the periphery of a desired pattern greatly affects a dimensional precision of the desired pattern in lithography and etching processes which are most important for achieving fine processing.
Then, mask correction technologies such as an optical proximity correction (OPC) and a process proximity correction (PPC) is developed in order to avoid those influences.
The aforementioned mask correction technologies are to add an auxiliary pattern in advance such that a dimension after processing is made to be a design pattern (desired value), or to make a width of a pattern broad or narrow (Jpn. Pat. Appln. KOKAI Publication No. 2003-107664, SPIE Vol. 2322 (1994) 374 (Large Area Optical Proximity Correction using Pattern Based Correction, D. M. Newmark et. al). In accordance therewith, it is possible to form an integrated circuit pattern which a designer has drawn on a wafer.
When the mask correction technologies are used, a technology for verifying validity of the correction is required. As this kind of technology, there is a method which verifies properness of correction based on a mask value. To carry out this method exactly, it is indispensable to use a (lithography) simulator.
To carry out a method that uses such a simulator, a verification tool is proposed. The verification tool compares an edge of a desired pattern on a wafer with an edge of a pattern transferred using a post OPC layout so that a difference between the two may be checked on whether it is in a predetermined tolerance (see Specification of U.S. Pat. No. 6,470,489).
Another method is proposed to highly accurately predict a displacement between an edge of a desired pattern and an edge of a transferred pattern by using proximity correction and a verification physical model (see Jpn. Pat. Appln. KOKAI Publication No. 09-319067).
These presently proposed methods grasp design data such as a line width, a space width, and a shortening quantity of a line edge in terms of a planar dimension (area) and are effective to detect an abnormal value of the line width.
On the other hand, to secure exposure latitude against the progressing miniaturization, a resist film used in an exposure process has been made thinner. The exposure latitude is an index for ensuring the predetermined allowable line width even if a dispersion in focus or exposure amount which are assumed to be occurred in an exposure apparatus or the like.
When a member (e.g., insulation film, conductive film, or semiconductor film) under a resist film is etched, the resist film is also etched. Therefore, if an initial resist film is too thin, such a problem occurs that the resist film may disappear before the etching finishes.
A thickness of developed resist film varies with exposure conditions or a layout of patterns around the resist film. Accordingly, recently there has been increasing needs for a technology to detect a pattern which may cause a problem due to a thin resist film, based on overall design data (whole patterns). However, presently such technology is not available.